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smm151/152 ? summit microelectronics, inc. 2007 ? 757 n. mary avenue ? sunnyvale ca 94085 ? phone 408 523-1000 ? fax 408 523-1266 http://www.summitmicro.com/ 2131 3.0 1/20/2010 1 single-channel voltage/current m onitors and voltage marginers introduction ? capable of margining supplies with trim inputs using either positive or negative trim pin control ? wide margin range of 0.3v to vdd with internal reference ? differential voltage sensing of the dc-dc converter output voltage ? supply-side current monitoring (10-bit adc) ? 10-bit adc readout of supply voltage over i 2 c bus ? margining controlled via: i 2 c command input pins (m up , m dn ) ? two programmable general purpose sensor inputs (comp1/2) ? uv/ov with fault output ? programmable glitch filters (comp1/2) ? programmable internal comp1/2 vref: 0.5v or 1.25v ? operates from 2.7v to 5.5v supply ? current sensing from 4.0v to 15v supply ? programmable, genera l purpose i/os (SMM152) ? general purpose 256-byte eeprom with write protect ? i 2 c 2-wire serial bus for programming configuration and monitoring status ? 28-lead 5x5 qfn applications ? in-system test and control of point-of-load (pol) ? power supplies for multi-voltage processors, dsps and asics ? routers, servers, storage area networks the smm151/152 are highly accurate power supply voltage/current supervisors and monitors with provisions for voltage margining of the monitored supply. the parts include an internal voltage reference to accurately monitor and margin the supply to within 1%. the smm151/152 have the capability to margin over a wide range from 0.3v to vdd using the internal reference and can read the differential voltage of the supply and voltage drop of the current sense resistor over the i 2 c bus using an on-chip 10-bit adc. the margin levels are set using the i 2 c serial bus. the devices initiate margining via the i 2 c bus or by using the m up or m dn inputs. once the pre- programmed margin target voltage is reached, the smm151/152 hold the converter at this voltage until receiving an i 2 c command or de-asserting the margin input pin. when the smm151/152 are not marginin g, the trim output pin is held in a high impedance state allowing the converter to operate at its nominal set point. two general purpose input pins are provided for sensing under or over-voltage conditions. a programmable glitch filter associated with these inputs allows the user to ignore spurious noise signals. a fault# pin is asserted once either input set point is exceeded. the SMM152 also provides four programmable general-purpose inputs/outputs. using the i 2 c interface, a host system can communicate with the smm151/152 status register and utilize 256-bytes of nonvolatile memory. typical application features & applications vm+ trim trim vout+ sen+ dc-dc converter vdd wp a0-a2 comp1 comp2 scl sda fault# capm+ mup mdn i 2 c interface margin commands v1 2.7v-5.5v smm151 (SMM152) ready gnd vdd_cap status outputs vout- sen- vm- 4.0v-15v vin cs- cs+ r s vref capm- capc (gpio0) (gpio1) (gpio2) (gpio3) figure 1 ? application with the smm151/152 used to monitor and margin a dc/dc converter. notes: r s must be kelvin sensed for maximum current sensing accuracy.t his is an applications example only. some components and values ar e not shown.
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 2 the smm151 and SMM152 are capable of margining the dc output voltage of ldos or dc/dc converters that use a trim/adjust pin. the margin function is programmable over a standard 2-wire i 2 c serial data interface and is used to set the margin low/high dc output voltages. the devices are also capable of monitoring the differential output voltage and the input current of dc/dc converters, thereby providing real-time power information to the system. in margining mode the user communicates with the smm151/152 via the i 2 c serial data bus to select the desired values for margining. this allows the part to margin the supplies up or down to these set values either through asserting the mup and mdn pins or by writing to the margin register directly. the margin high and margin low voltage settings can range from 0.3v to vdd around the converter?s nominal output voltage setting depending on the specified margin range of the dc-dc converter and/or syst em components, usually 10%. the smm151/152 also feature a margin nominal command and set-point. this can be used to set the converter's nominal output voltage to a more accurate value than is attainable without margining due to inaccuracy of the standalo ne converter and its voltage setting components. when the smm151/152 receive the command to margin, the trim output will begin adjusting the supply to the selected margin voltage. this is accomplished by incrementing (or decrementing) an internal counter based on the digital comparison between the voltage margin target value and that read by the adc from the vm+ - vm- differential input. this operation is repeated until the 2 values are equal, after which the smm151/152 hold the trim output pin at the voltage required to maintain the margin setting. an i 2 c command or de-assertion of the mup/mdn pin will return the trim output pin to a high impedance state thus allowing the converter to return to its nominal operating voltage. the smm151 and SMM152 sense converter input current using a kelvin connected sense resistor in series with the converter supply whose terminals are connected to the cs+ and cs- pins. the internal adc, also used for measuring the converter?s output voltage, is used to measure the converter?s input current using the voltage dropped across the current sense resistor r s (see figure 1). the smm151/152 have two additional input pins and one additional output pin. the input pins, comp1 and comp2, are high impedance inputs, each connected to a comparator and compared against the internal reference (vref: 0.5v or 1.25v). each comparator can be independently programmed to monitor for uv or ov. when either of the comp1 or comp2 inputs are in fault the open-drain fault# output will be pulled low. a configuration option exists to disable the fault# output during margining. the SMM152 also provides four programmable general- purpose inputs/outputs. the power-on state of these i/os is determined via non-volatile (nv) memory. volatile programming allows the user to select the logic level (high or low) of each i/o, which can also be read via a status register. programming of the smm151/15 2 is performed over the industry standard i 2 c 2-wire serial data interface. a status register is available to read the state of the part and a write protect (wp) pin is available to prevent writing to the configuration registers and ee memory. general description
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 3 vm+ control logic trim 10bit adc digital comparator 8-bit dac i 2 c interface clock up/dn halt margin target ov /uv ov /uv output control vdd wp a0 a1 a2 comp1 comp2 scl sda fault# ee configuration registers & memory gnd glitch filter sw1 sw2 mux capm+ mup mdn ready vref = 1.25v 50k 50k vref vm- cs+ cs- diff am p vref v dd_cap capc 25k 25k capm- 250k gpio0 gpio1 control logic gpio2 gpio3 SMM152 0.5v/1.25v figure 2 ? smm151 and SMM152 contro ller internal block diagram. package and pin description internal block diagram
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 4 pin number pin type pin name pin description 28 i/o sda i 2 c bi-directional data line 1 i scl i 2 c clock input. 2 i a2 4 i a1 6 i a0 the address pins are biased either to vdd, gnd or left floating. this allows for a total of 21 distinct device addresses. when communicating with the smm151/2 over the 2-wire bus thes e pins provide a mechanism for assigning a unique bus address. i/o gpio0,1,2,3 SMM152: general purpose inputs/outputs. 3, 9, 22, 27 nc nc smm151: no connect. 8 i wp programmable write protect active high/ low input. when asserted, writes to the configuration registers and general purpose ee are not allowed. the wp input is internally tied to vdd with a 50k resistor. 10, 13 cap capm+, - external capacitor inputs used to filter the vm+/vm- inputs, 0.22 f. 20 o trim output voltage used to control and/or margin converter voltages. connect to the converter trim input. 14 i vm+ voltage monitor input. connect to the dc-dc converter positive sense line or its +vout pin. 15 i vm- voltage monitor input. connect to the dc-dc converter negative sense line or its -vout pin. 18 i cs+ current monitor input + side. kelvin connect to the input supply side of the current sense resistor. 17 i cs- current monitor input - side. kelvin connect to the load side of the current sense resistor. 26 pwr vref internal reference voltage of 1.25v . connect to gnd through a 0.1uf capacitor to improve noise immunity. 16 o capc external capacitor input used to filter the cs+/cs- input. typical value: 1uf. 21 pwr vdd power supply of the part. 23 pwr vdd_cap external capacitor input used to filter the internal vdd supply rail. 7 gnd gnd ground of the part. the smm151/2 ground pin should be connected to the ground of the device under control or to a star point ground. pcb layout should take into consideration ground drops. 24 i mup margin up command input. asserted high. the mup input is internally tied to vdd with a 50k resistor. 25 i mdn margin down command input. asserted high. the mdn input is internally tied to vdd with a 50k resistor. 19 i comp1 12 i comp2 comp1 and comp2 are high impedance inputs, each connected internally to a comparator and compared against the internally programmable vref voltage. each comparator can be in dependently programmed to monitor for uv or ov. the monitor level is set externally with a resistive voltage divider. 11 o fault# when either of the comp1 or comp2 inputs are in fault the open-drain fault# output will be pulled low. a co nfiguration option ex ists to disable the fault# output while the device is margining. pin descriptions
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 5 pin descriptions (continued) 5 i/o ready programmable active high/low open drai n output indicates that vm+ - vm- is at its set point. when programmed as an active high output, ready can also be used as an input. when pulled low, it will latch the state of the comparator inputs. 29 gnd gnd gnd. the bottom side metal plate (pad 29) should be connected on the pcb to gnd for optimized noise performance. 1 28 21 20 19 18 17 16 15 22 23 24 25 26 27 2 3 4 5 6 7 14 13 smm150 pin 1 scl a2 (gpio0) a1 ready a0 gnd wp (gpio1) capm+ fault# capm- comp2 vm+ vdd trim comp1 cs+ cs- capc vm- sda (gpio3) vref mdn mup vdd_cap (gpio2) 12 11 10 9 8 28-pad 5x5 qfn top view () applies on SMM152 pin configuration
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 6 absolute maximum ratings recommended operating conditions temperature under bi as .................................- 55c to 125c storage temperature qf n ..............................-65c to 150c terminal voltage with respect to gnd: vdd supply voltage .................................. -0.3v to 6.0v all other s ....................................... -0.3v to v dd + 0.7v fault#???????????.???. gnd to 15.0v cs+, cs-...????????????? -0.3v to 16.0v output short circu it curre nt ........................................ 100ma reflow solder temperature (10 secs) .......?.???....240c junction temperature........... ..............??. ....???....150c human body esd rating per jedec??..????....2000v machine model esd rating per jedec??..????..200v latch-up testing per jedec???..??...???.? 100ma temperature rang e (industria l)..................... ?40c to +85c (commerc ial) ..................... 0c to +70c cs+, cs- ............................................................. 4. 0v to 15v vdd supply voltage ........................................... 2.7v to 5.5v inputs ..................................................................gnd to vdd package thermal resistance ( ja ) 28-pad qfn (thermal pad connected to pcb)???37.2 o c/w 28-pad qfn (thermal pad not connected to pcb).?66.5 o c/w moisture classification level 3 (msl 3) per j-std- 020 reliability characteristics data retention???????????..????.?20 years endurance?????????.??????...100,000 cycles note - the device is not guaranteed to function outside its operating rating. stresses listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not im plied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. devices are esd sensitive. h andling precautions are recommended. dc operating characteristics t a = 0 c to +70 c, vdd = 2.7v to 5.5v, vcs = 4.0v to 15v, unless otherwi se noted. all voltages are relative to gnd. note 6. symbol parameter notes min. typ. max unit vdd supply voltage 2.7 3.3 5.5 v vm+ pin voltage range, note 5 -0.3 vdd v vm range sense voltage common mode range vm- pin voltage range, note 5 -0.3 +0.5 v cs range current sense common mode voltage range cs+, cs- pin voltage range 4.0 15 v i dd supply current from vdd trim pin floating 3 ma trim sourcing current, note 5 1.5 ma i trim max. trim output current through 100 to 1.0v trim sinking current, note 5 -1.5 ma v trim trim output voltage range i trim 1.5ma, note 5 gnd 2.5 v v adoc margin range depends on converter trim range 0.3 vdd v vdd = 2.7v 0.9xvdd vdd v ih input high voltage sda, scl, wp, mup, mdn vdd = 5.0v 0.7xvdd vdd v vdd = 2.7v 0.1xvdd v il input low voltage sda, scl, wp, mup, mdn vdd = 5.0v 0.3xvdd v v ol open drain output fault#, gpiox, ready isink = 1ma 0.2 v vdd = 2.7v, r pullup 300k 0.9xvdd vdd v aih address input high voltage, a2, a1, a0 vdd = 5.0v, r pullup 300k 0.7xvdd vdd v vdd = 2.7v, r pulldown 300k 0.1xvdd v ail address input low voltage, a2, a1, a0 vdd = 5.0v, r pulldown 300k 0.3xvdd v
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 7 dc operating characteristics (continued) t a = 0 c to +70 c, vdd = 2.7v to 5.5v, vcs = 4.0v to 15v, unless otherw ise noted. all voltages are relative to gnd. note 6. symbol parameter notes min. typ. max unit i ait address input tristate maximum leakage ? high z -3.0 +3.0 a ov/uv monitor voltage range comp1 and comp2 pins 0 vdd v v hyst comp1/2 dc hysteresis comp1 and comp2 pins, v th -v tl (see note 1) 10 mv r pull-up input pull-up resistors see pin descriptions, note 5 50 k vref=1.25v 1.24 1.25 1.26 vref internal comp1/2 reference vref=0.5v 0.495 0.500 0.505 v vm+ - vm- = 1.2v, note 4 -1.0 0.75 +1.0 % marg acc margin accuracy vm+ - vm- = 2.5v, note 4 -1.0 0.75 +1.0 % vm adc voltage monitor adc measure range vm+ - vm- 0 vdd v r vm vm+, vm- input resistance note 5 50 k cmrr vm voltage sense common mode rejection ratio v cm (vm+, vm-) = 0.5v ? vdd, note 5 62 db minimum cs+ - cs- voltage 0 cs adc current monitor adc measure range maximum cs+ - cs- voltage 100 mv cs adc 50mv, note 2 -2 +2 % cs acc current sense accuracy cs adc < 50mv, note 2 -1 +1 mv v cm (cs+, cs-) = 5.0v, note 5 100 cmrr cs current sense common mode rejection ratio v cm (cs+, cs-) = 12v, note 5 80 db note 1: v hyst is measured with a 1.25v external voltage and is determi ned by subtracting threshold low from threshold high, v th -v tl while monitoring the fault# pin state. actual dc hysteresis is derived from the equation: (v in(comp1/2) /v ref )( v hyst ). for example, if v in(comp1/2) /=2.5v and v ref =1.25v then actual dc hysteresis= (2.5v/1.25v)(0.003v)=6mv. note 2: current sense accuracy depends on the current sense resi stor tolerance. kelvin sensing of the voltage drop across this resistor must be used to guarantee accuracy. accuracy at the low range of the cu rrent monitor adc will be adversely impacted by offset errors. note 3: it is recommended that adc reads occur with a frequency of not more than 250hz. note 4: voltage accuracy is only guaranteed for factory-programme d settings. changing voltage from the value reflected in the c ustomer specific csir code may result in inaccuraci es exceeding those specified above. note 5: not 100% production tested. guaranteed by design and/or characterization. note 6: all electrical parameters are guar anteed to function over the stated vdd, vcs and temperature range. electrical paramet ers not specified as "guaranteed by design" are tested with a vdd voltage required of the specific application. for ex ample, if the device is to be operated at 3.3v and vcs supply of 12v, it is tested with a vdd supply of 3.3v, +-10% and a vcs supply of 12v, +-10%.
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 8 ac operating characteristics t a = 0 c to +70 c, vdd = 2.7v to 5.5v unless otherwise noted. all voltages are relative to gnd. symbol parameter notes min. typ. max unit t adc_dac monitor sampling/conversion period update period for adc conversion and dac update 1.8 ms t marg_i/d margin single bit increment or decrement time t marg_update = (x)(1.8ms) where: x=step number of possible 256 steps and 1 step=10mv 1.8 ms t glitch_mu/d margin up/down glitch filter 70 100 130 s 0 ms 10 ms 20 ms 40 ms 80 ms 100 ms 120 ms t glitch_comp programmable comp1 & comp2 glitch filter times 140 ms 2.5 ms 5 ms 10 ms t margin programmable margin delay times see figure 4 17.5 ms
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 9 i 2 c 2-wire serial interface ac ope rating characteristics ? 100khz t a = 0 c to +70 c, vdd = 2.7v to 5.5v unless otherwise noted. all voltages are relative to gnd. see figure 3 timing diagram. note 6. symbol description conditions min typ max units f scl scl clock frequency 0 100 khz t low clock low period 4.7 s t high clock high period 4.0 s t buf bus free time before new transmission, note 5 4.7 s t su:sta start condition setup time 4.7 s t hd:sta start condition hold time 4.0 s t su:sto stop condition setup time 4.7 s t aa clock edge to data valid scl low to valid sda (cycle n) 0.2 3.5 s t dh data output hold time scl low (cycle n+1) to sda change 0.2 s t r scl and sda rise time note 5 1000 ns t f scl and sda fall time note 5 300 ns t su:dat data in setup time 250 ns t hd:dat data in hold time 0 ns ti noise filter scl and sda noise suppression 100 ns t wr write cycle time 5 ms note 5: not 100% production tested. guaranteed by design and/or characterization. note 6: all electrical parameters are guar anteed to function over the stated vdd, vcs and temperature range. electrical paramet ers not specified as "guaranteed by design" are tested with a vdd voltage required of the specific application. for ex ample, if the device is to be operated at 3.3v and vcs supply of 12v, it is tested with a vdd supply of 3.3v, +-10% and a vcs supply of 12v, +-10%. timing diagrams t r t f t high t low t su:sta t hd:sta t su:dat t hd:dat t su:sto t buf t dh t aa scl sda (in) sda (out) t wr (for write operation only) figure 3. basic i 2 c serial interface timing
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 10 device operation power supply the smm151 and SMM152 can be powered by a 2.7v to 5.5v input to the vdd pin (figure 1). see figure 6 as an example. voltage reference the smm151/152 use an internal voltage reference, vref with a level of 1.25v. total accuracy of vref is 1.0% over temperature and supply variations. modes of operation the smm151/152 have four basic modes of operation: under-voltage (uv) and over-voltage (ov) monitoring mode, differential output voltage sensing mode, input current monitoring mode and supply margining mode. a detailed description of each mode and feature follows and can also be found in application note 68. a flow diagram is shown in figure 5. margin mode the smm151/152 can control margining of a dc/dc converter that has a trim pin or any regulator having access to its feedback node. the trim pin on the smm151 is connected to the trim input pin on the power supply converter. sense lines from the converter?s point-of-load connects to the vm+ and vm- inputs. the margin function begins upon an i 2 c command or assertion of the mup/mdn pins. the trim pin is driven by a dac whose input is incremented or decremented every 200s based on the digital comparison of the margin target value and the actual converter output voltage. the voltage on the trim output will continue increasing or decreasing until the converter?s output voltage equals the target margin voltage. this voltage adjustment allows the smm151 and SMM152 to control the margined output voltage of the power supply converter to within 1.0% in an open-loop manner. the converter is held at the margin voltage until the smm151 receives an i 2 c command or the respective mup/mdn pin is de-asserted. when not margining, the trim pin on the smm151/152 is in a high impedance state. the voltage on the trim pin is buffered and applied to the adc at the beginning of a margin cycle to ensure the converter is margined from its nominal setpoint. this allows a smooth transition from the converter?s nominal voltage to the smm151/152 controlling that margin voltage to the margin target setting. afte r margining high, low or nominal, issuing a margin off command will cause the trim pin to go high impedance. the part margin time from off to high or off to low is specified as a typical according to the equation: t marg_update = (x)(1.8ms) where: x=number of possible steps (256) and 1 step = 10mv the active margin command delay time using the mup and mdn pins is shown in figure 4. dc/dc supply gnd smm151 mpu/d/en total margin delay time margin n/h/l t adc_dac adc/dac sample/ conversion time 1.8ms 1.8ms t margin_update t margin - internal programmable active margin delay time turn on time t adc_dac adc/dac sample/ conversion time figure 4 ? margin delay time applications information
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 11 yes power ok? margining operation 1. hold dac 2. clear status register 3. wait for next command input vtrim to adc no dump adc into dac dac drives brick (trim output lo-z) input vout to adc no adc equal target? yes increment/ decrement dac figure 5 - smm151/152 margin flow chart applications information (continued)
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 12 when measuring the margin delay time external to the device, adc sample time and update trim time ( ? 3.6 ms) must be added to the internally programmed delay time as shown: spec actual measurement 2.5 ms 6.1 ms 5 ms 8.6 ms 10 ms 13.6 ms 17.5 ms 21.1 ms monitor the smm151/152 monitor the comp1 and comp2 pins. comp1 and comp2 are high impedance inputs, each connected internally to a comparator and compared against the programmable internal reference voltage. each comparator can be independently programmed to monitor for either an uv or an ov event. the monitor level may be set externally with a resistive voltage divider. the compx pins can be connected to vin, vout or any voltage that needs to be monitored. the internal comparators comp1/2 are compared to vref, so the voltage dividers are set above or below the programmed vref level depending on whether monitoring uv or ov. as an example, with vref set to 1.25v, to monitor an ov of 1.7v on comp1 and a uv of 1.3v on comp2, the voltage divider resistors are: for ov, rupper = 1.37k, 1% rlower = 3.83k, 1%. for uv, rupper = 1.02k, 1% rlower = 25.5k, 1%. the parts can be programmed to trigger the fault# pin when either compx comparator has exceeded the uv or ov setting. the ready and fault# outputs of the smm151/152 are active as long as the triggering limit remains in a fault condition. the ready pin is a programmable active high/low open drain output indicates that vm+ - vm- is at its? set point. when programmed as an active high output, ready can also be used as an input. when pulled low, it will latch the state of the comparat or inputs. when either of the comp1 or comp2 inputs are in fault, the open- drain fault# output will be pulled low. a configuration option exists to disable the fault# output while the device is in margining mode. general-purpose inputs/outputs the gpios are open drain type outputs. the pins should be pulled up externally to voltages ranging from 2.0v to 12v. each i/o has non-volatile (nv) memory setting associated with it that determines the power-on state of the pin. the status (high/low) is read from bit 0 of registers 34h, 35h, 36h or 37h with 0=low and 1=high. additionally, the i/os have a command bit that when written overrides the nv setting and sets the pin either high or low. the i/os also have status bits to read the state of the pin as high or low. the command/status register for each i/o is addressed separately alleviating the need for the host controller to remember the state of t he other i/os when writing commands. more information can be found in application note 69. status register a status register exists for i 2 c polling of the status of the comp1 and comp2 inputs. tw o bits in this status register reflect the current st ate of the inputs (1 = fault, 0 = no fault). two additional bits show the state of the inputs latched by one of tw o events programmed in the configuration. more information can also be found in application note 69. the first event option is the fault# output going active. the second event option is the ready pin going low. the ready pin is an i/o. as an output, the ready output pin goes active when the dc controlled voltages are at their set point. as an input programmed to active high, it can be pulled low externally and latch the stat e of the comp inputs. this second event option allows the state of the comp inputs on multiple devices to be latched at the same time while a host monitors their fault# outputs. margining the smm151/152 have three additional control voltage settings: margin high, margin nominal, and margin low. the margin high and margin low settings can be as much as 15% of the nominal setting depending on the converter manufacturer. the margin high and margin low voltage settings can range from 0.3v to vdd around the converters? nominal output voltage setting depending on the specified margin range of the dc-dc converter. these settings are stored in the configuration registers and are loaded as control voltage settings by margin commands issued via the i 2 c bus. the margin command registers contain two bits that decode the commands to margin high or margin low. once the smm151/152 receive the command to margin the supply voltage, it begins adjusting the supply voltage to move toward the desired setting. when this voltage setting is reached, a bit is set in the margin status registers and the ready signal becomes active. note: configuration writes or reads of registers 00 hex to 03 hex should not be performed while the smm151 or SMM152 is margining. applications information (continued)
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 13 faults when either of the comp1 or comp2 inputs are in fault, the open-drain fault# output will be pulled low. a configuration option exists to disable the fault# output while the device is margining. if ?fault output disabled while margining? is selected, faults are disabled for all margining except when margining to the ?off? and ?nominal? states. also, the programmable feature ?fault holds off and shutdown control? is enabled only for the nominal margin state. please note that if "fault output disabled? is selected and the device has margined to low and high and then returns to the off state without going through nominal, the status register will read a fault (if there is one) but the fault output pin will be disabled until such time that the nominal setting is activated. to avoid this condition it is recommended that the device always return to off from the nominal state. fault latched by a fault condition: the ?fault latched by a fault condition? programmable option is triggered only on the leading edge of a fault. that is, a latched fault can be cleared while the fault yet exists. fault latched by ready i/o pin: fault latched by ready i/o pin functions on the margin transitions from off to hi/low/nominal or from nominal to hi/low or hi/low to nominal but not from hi/low/nominal to off. write protection write protection for the smm151/152 is located in a volatile register where the power-on state is defaulted to write protect. there are separate write protect modes for the configuration registers and memory. in order to remove write protection, the code 55 hex is written to the write protection register.o ther codes will enable write protection. for example, writing 59 hex will allow writes to the configuration register but not to the memory, while writing 35 hex will allow writes to the memory but not to the configuration register s. the smm151/152 also feature a write protect pin (wp input) which, when asserted, prevents writing to the configuration registers and ee memory. in addition to these two forms of write protection there is a configuration register lock bit which, once programmed, does not allow the configuration registers to be changed. a2, a1, a0 the address bits a[2:0] can be hard wired high or low or may be left open (high-z) to allow for a total of 21 distinct device addresses. when floating, the inputs can tolerate the amount of leakage as described by the specification i ait . an external 100k pull-up or pull down resistor is sufficient to set a high or low logic level. cs+, cs- select a resistor value that will drop no more than 100mv (full scale) when full load is drawn by the converter or circuit being sensed by the resistor r s (figure 1). to obtain highest accuracy current-sensing, provide a kelvin connection from the resistor to the cs+ and cs- pins. do not allow the main current path circuit traces to inadvertently become a part of the current sense resistor. kelvin connect directly at the resistor and follow the manufacturer?s instructions for exact positioning of the traces for kelvin sensing. applications information (continued)
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 14 figure 6 ? typical application schematic shows the sm m151 controlling a 12v in/1.5 v out dc/dc converter. this example, using the 1.25v vref, also shows the comp 1/2 pins monitoring the dc/dc converter vout set to an ov of 1.7v on comp1 and a uv of 1.3v on comp2, the volt age divider resistors are: for ov, r1 = 1.37k, 1% r3 = 3.83k, 1%, for uv, r2 = 1.02k, 1% r4 = 25.5k, 1%. the programming supply jumper can be used to supply the smm151 vdd voltage from the smx3202 programmer when th e device is programmed with board power off and the controlled supply unloaded. c4 0.47uf fault# ready vout = 1.5v r6 0.01, 1% vdd r1 1.37k, 1% r2 1.02k, 1% r3 3.83k, 1% r4 25.5k, 1% +vout 1 +sense 2 -sense 3 -vout 4 gnd 5 gnd 6 +vin 7 +vin 8 +vin 9 trim 10 enable 11 u2 dc-dc sie c8 0.01uf c9 0.01uf mup c3 10uf c12 c load c1 0.01uf c10 0.1uf c11 0.01uf vdd mdn c2 0.1uf scl 1 a2 2 nc 3 a1 4 ready 5 a0 6 gnd 7 wp# 8 nc 9 capm+ 10 fault# 11 comp2 12 nc 22 vm+ 14 nc 27 capm- 13 cs- 17 cs+ 18 comp1 19 trim 20 vdd 21 capc 16 vm- 15 mup 24 mdn 25 vdd_cap 23 vref 26 sda 28 u1 smm151 r7 r load gnd 1 scl 2 gnd3 3 sda 4 rsrv5 5 mr 6 +10v 7 rsrv8 8 +5v 9 rsrv10 10 j1 i2c 1 2 programming supply 12vin +vin 2.7v- 5.5v vdd r5 2.5k c6 0.22uf vdd c5 1uf c7 0.1uf d1 diode applications information (continued)
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 15 maximizing accuracy maximum margining accuracy is obtained by placing a resistor between the smm151/152 trim output and the trim input of the converter. from the manufacturer?s data sheet obtain the value of the internal voltage reference and equivalent trim input series resistance. figure 7 below displays the internal trimming circuit for a typical isolated dc-dc converter. in this example, the converter uses positive trimming, i.e., an increase in voltage at the trim pin causes an increase in output voltage. dc-dc converter trim vref v- v+ -s +s l o a d vref r trim smm151/152 trim pin r1 r2 figure 7 - simplified trim circuit of an isolated dc-dc converter connects to smm151/152 trim output for this example r trim is found: () () () -0.3 2 ( -0.3) = -0.3 1- -0.3 trim vref k r vref r k vref vref ?? ?? ?? where: nom low v v k = 0.3 = smm151/152 trim output saturation voltage vlow = margin low target voltage vnom = nominal (non-trimmed output voltage) vref = converter internal reference voltage the next example applies to most non-isolated dc-dc converters, ldo?s and in-system designed converters using monolithic pwm controllers. figure 8 is a simplified schematic showing the resistor divider network used to close the loop from the output to the circuit?s feedback node. these type circuits employ negative trimming, meaning any decrease in voltage into the feedback node c ause an increase in output voltage. ( ) () 1 - 0 . 3 = -1 trim r vref r vnom k nom high v v k = 0.3 = smm151/152 trim output saturation voltage vhigh = margin low target voltage vnom = nominal (non-trimmed output voltage) vref = converter internal reference voltage applications information (continued)
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 16 vout to fb node (vref) r trim smm151/152 trim pin r1 r2 figure 8 - simplified trim circuit of a non-isolated dc-dc converter connects to smm151/152 trim output applications information (continued)
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 17 the end user can obtain the summit smx3202 programming system for device prototype development. the smx3202 system consists of a programming dongle, cable and windows tm gui software. it can be ordered on the website or fr om a local representative. the latest revisions of all software and an application brief describing the smx3202 is available from the website ( www.summitmicro.com ). the smx3202 programming dongle/cable interfaces directly between a pc?s usb port and the target application. the device is t hen configured on-screen via an intuitive graphical user interface employing drop- down menus. the windows gui software will generate the data and send it in i 2 c serial bus format so that it can be directly downloaded to the smm151/152 via the programming dongle and cable. an example of the connection interface is shown in figure 9. when design prototyping is complete, the software can generate a hex data file that should be transmitted to summit for approval. summit will then assign a unique customer id to the hex code and program production devices before the final electr ical test operations. this will ensure proper devic e operation in the end application. pin 9, 5v pin 7, 10v pin 5, reserved pin 3, gnd pin 1, gnd pin 6, mr# pin 4, sda pin 2, scl pin 8, reserved pin 10, reserved top view of straight 0.1" x 0.1 closed-side connector. smx3202 interface cable connector. 9 7 5 3 1 10 8 6 4 2 smm151 SMM152 sda scl vdd gnd 0.1 f common ground wp d1 c1 1n4148 positive supply jumper figure 9? smx3202 programmer i 2 c serial bus connections to program the smm151/152. the smm151/152 have a write protect pin (wp input) which, when asserted, prevents writing to the configuration registers and ee memory. in addition, there is a configuration register lock bit, which, once programmed, does not allow the configuration registers to be changed. applications information (continued)
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 18 i 2 c programming information serial interface access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standar d 2-wire serial interface (i 2 c). sda is a bi-directional data line and scl is a clock input. data is clocked in on the rising edge of scl and clocked out on the falling edge of scl. all data transfers begin with t he most significant bit (msb). during data transfers sda must remain stable while scl is high. data is transferred in 8-bit packets with an intervening clock period in which an acknowledge is provided by the device receiving data (smm151). the scl high period (t high ) is used for generating start and stop conditions that precede and end most transactions on the serial bus. a high-to-low transition of sda while scl is high is considered a start condition while a low-to-high transition of sda while scl is high is considered a stop condition. the interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. the address byte is comprised of a 4-bit device type identifier (slave address) and a unique (three-state) 3-bit bus address. the remaining bit indicates either a read or a write operation. refer to table 1 for a description of the address bytes used by the smm151/152. refer to table 2 for an example of the unique address handling of the smm151/152. the device type identifier for the memory array, the configuration registers an d the command and status registers are accessible with the same slave address. it can be set using the address pins as described in table 2. the bus address bits a[2:0] are hard wired only through address pins 2, 4 and 6 (a2, a1 and a0 respectively) or may be left open (z) to allow for a total of 21 distinct device addresses. the bus address accessed in the address byte of the serial data stream must match the setting on the smm151 address pins. write writing to the memory or configuration registers is illustrated in figures 10, 11, 12, 14, 15 and 17. a start condition followed by the address byte is provided by the host i 2 c controller; the smm151 responds with an acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the smm151/152 respond with an acknowledge; the host then clocks in one byte of data. for memory and configuration r egister writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive a ddresses within the same page. after the last byte is clocked in and the host receives an acknowledge, a stop condition must be issued to initiate the nonvolatile write operation. read the address pointer for the configuration registers, memory, command and status registers and adc registers must be set before data can be read from the smm151. this is accomplished by issuing a dummy write command, which is simply a write command that is not followed by a stop condition. the dummy write command sets the address from which data is read. after the dummy write command is issued, a start command followed by the address byte is sent from the host. the host then waits for an acknowledge and then begins clocking data out of the slave device (smm151/2). the first byte read is data from the address pointer set during the dummy write command. additional bytes can be clocked out of consecutive addresses with the host providing an acknowledge after each byte. after the data is read from the desired registers, the read operation is terminated by the host holding sda high during the acknowledge clock cycle and then issuing a stop condition. refer to figures 13, 16 and 18 for an illustration of the read sequence. write protection the smm151/152 power up into a write protected mode. writing a code to the volatile write protection register (write only) can di sable the write protection. the write protection register is located at address 38 hex . writing to the write protection register is shown in figure 10. writing 0101 bin to bits [7:4] of the write protection register allows writes to the general-purpose memory while writing 0101 bin to bits [3:0] allow writes to the configuration registers. write protection isre-enabled by writing other codes (not 0101 bin ) to the write protection register.
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 19 i 2 c programming information (continued) configuration registers the majority of the configuration registers are grouped with the general-purpose memory. writing and reading the configuration registers is shown in figures 11, 12 and 13. note: configuration writes or reads of registers 00 to 03 hex must not be performed while the smm151/152 is margining. general-purpose memory the 256-byte general-purpose memory is located at any slave address. the bus address bits are hard wired by the address pins a2, a1 and a0. they can be tied low, high or left floating, (hi-z). memory writes and reads are shown in figures 14, 15 and 16 . command and status registers writes and reads of the command and status registers are shown in figures 17 and 18. graphical user interface (gui) device configuration ut ilizing the windows based smm151/152 graphical user interface (gui) is strongly recommended. the software is available from the summit website ( www.summitmicro.com ). using the gui in conjunction with this datasheet simplifies the process of device prototyping and the interaction of the various functional blocks. a programming dongle (smx3202) is available from summit to communicate with the smm151/152. see figure 9 and the smx3202 data sheet ( www.summitmicro.com ). slave address bus a ddress register type configuration registers are located in 00 hex thru 05 hex and 30 hex thru 3e hex 10xx a2 a1 a0 general-purpose memory is located in 40 hex thru ff hex table 1 - address bytes used by the smb151/152. slave address programmed as 10xx (z = hi-z state) pins a[2:0] a2 a1 a0 slave address bus address 0 0 0 1000 000 0 0 1 1000 001 0 0 z 1000 010 0 1 0 1000 100 0 1 1 1000 101 0 1 z 1000 110 0 z x 1000 011 1 0 0 1001 000 1 0 1 1001 001 1 0 z 1001 010 1 1 0 1001 100 1 1 1 1001 101 1 1 z 1001 110 1 z x 1001 011 z 0 0 1010 000 z 0 1 1010 001 z 0 z 1010 010 z 1 0 1010 100 z 1 1 1010 101 z 1 z 1010 110 z z x 1010 011 table 2 ? example device addresses allowed by the smm151.
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 20 i 2 c programming information (continued) s t a r t w a c k master slave a c k configuration register address = 38 hex 0 0111000 0 1010101 s t o p data = 55 hex a c k a 2 bus address a 1 a 0 5 hex unlocks general purpose ee 5 hex unlocks configuration registers write protection register address 10 s a 1 s a 0 3 hex 8 hex figure 10 ? write protection register write s t a r t bus address w a c k master slave a c k configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k a 2 a 1 a 0 10 s a 1 s a 0 figure 11 ? configuration register byte write s t a r t bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master master slave slave a c k data (16) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k a 2 a 1 a 0 10 s a 1 s a 0 figure 12 ? configuration register page write
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 21 i 2 c programming information (continued) s t a r t bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k bus address a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a 2 a 1 a 0 10 s a 1 s a 0 a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 13 - configuration register read s t a r t bus address w a c k master slave a c k configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k a 2 a 1 a 0 10 s a 1 s a 0 figure 14 ? general purpose memory byte write bus address s t a r t w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master master slave slave a c k data (16) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k a 2 a 1 a 0 10 s a 1 s a 0 figure 15 - general purpose memory page write
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 22 i 2 c programming information (continued) s t a r t w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) bus address bus address a 2 a 1 a 0 10 s a 1 s a 0 a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 16 - general purpose memory read s t a r t w a c k master slave a c k command and status register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k bus address a 2 a 1 a 0 10 s a 1 s a 0 figure 17 ? command and status register write s t a r t w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) command and status register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) bus address bus address a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 a 2 a 1 a 0 10 s a 1 s a 0 figure 18 - command and status register read
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 23 28-pad qfn package outlines
smm151/152 summit microelectronics, inc 2131 3.0 1/20/2010 24 smm151n l ayyww pin 1 nnnn summit part number date code (yyww) part number suffix (contains customer specific ordering requirements) lot tracking code (summit use) drawing not to scale ss status tracking code (blank, ms, es, 01, 02,...) (summit use) 100% sn, rohs compliant summit notice note 1 - this is a final data sheet that descr ibes a summit product currently in production. summit microelectronics, inc. reserves the ri ght to make changes to the products contai ned in this publication in order to impr ove design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits describ ed herein, conveys no license under any patent or other right, and ma kes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect repres entative operating parameters, and may vary depending upon a user?s specific application. while the info rmation in this publication has been care fully checked, summit microelectronics, inc . shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can r easonably be expected to cause any failure of either system or to significantly affe ct their safety or effectiveness. products are not authorized for use in such applications un less summit microelectronics, inc. receive s written assurances, to its satisfaction, that: (a) the risk of in jury or damage has been minimized; (b) the user assumes all su ch risks; and (c) potential liability of summit microelectronics, in c. is adequately protected under the circumstances. revision 3.0 - this document supersedes all previous versions . please check the summit microelectronics inc. web site at www.summitmicro.com for data sheet updates. ? copyright 2008 summit microelectronics, inc. programmable power for a green planet? i 2 c is a trademark of philips corporation part marking ordering information subject to change smm151 n nnnn package part number suffix summit part number customer specific requirements are contained in the suffix such as hex code, hex code revision, etc. (default csirs: smm151=786, SMM152=957) c temp range c=commercial blank=industrial n=28 pad qfn l: lead-free attribute for qfn package l smm151 or SMM152

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